2010.08-2013.09   法国国立高等电信学校（TELECOM Paris，IP Paris），博士研究生

2013-2015   法国国立高等电信学校，博士后

2015-2018   法国国立高等电信学校，助理教授

2018-2023   bevictor伟德官网，副教授，副研究员

2024-至今  bevictor伟德官网，教授

本科生课程：集成电路导论（B6300010）、人工智能通识导论（B6300040）、集成电路设计综合课程设计（B6308880），研究生课程：数字集成电路设计与EDA（MS404267）

[1] H. Du, Y. Wang, J. Yang and H. Cai*, Intrinsic MRAM Properties Enable Security Circuits, IEEE Trans. on Circuits and Systems II: Express Briefs, 71(3): 1695-1700, 2024.

[2] J. -L. Cui, Y. Guo, J. Chen, B. Liu and H. Cai*, Sparsity-Oriented MRAM-Centric Computing for Efficient Neural Network Inference, IEEE Trans on Emerging Topics in Computing, 12(1): 97-108, 2024.

[3] Y. Hou et al. H. Cai*, Q. Huang* and R. Huang, A Sub-100nA Ultra-low Leakage MCU Embedding Always-on Domain Hybrid Tunnel FET-CMOS on 300mm Foundry Platform, 2023 International Electron Devices Meeting (IEDM).

[4] H. Cai* et al, 33.4 A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference, 2023 IEEE International Solid-State Circuits Conference (ISSCC).

[5] H. Cai*, X. Tong, P. Wu, X. Liu, B. Liu, Bit-error-rate aware sensing-error correction interaction in spintronic MRAM, Journal of Systems Architecture, 2022: 102557.

[6] H. Cai* et al, Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell,IEEE Trans. on Circuits and System-I: Regular Papers, 69(4): 1519-1531, 2022.

[7] H. Cai* et al, Commodity Bit-Cell Sponsored MRAM Interaction Design for Binary Neural Network, IEEE Trans. on Electron Devices, 2022, 69(4): 1721-1726.

[8] H Cai* et. al., Toward Energy-Efficient STT-MRAM Design with Multi-Modes Reconfiguration, IEEE Trans. on Circuits and Systems II: Express Briefs, vol. 68, no. 7, pp. 2633-2639, 2021.

[9] Y Zhou, H Cai*, L Xie, M Han, M Liu, S Xu, B Liu, W Zhao, J Yang: A self-timed voltage-mode sensing scheme with successive sensing and checking for STT-MRAM,IEEE Trans. on Circuits and System-I: Regular Papers, 67(5): 1602-1614, 2020.

[10] Y Zhou, H Cai*et al: MTJ-LRB: Proposal of MTJ-based loop replica bitline as MRAM device-circuit interaction for PVT-robust sensing, IEEE Trans. on Circuits and Systems II: Express Briefs, 67(12): 3352-3356, 2020.

[DATE'2026].11/2025: The three MRAM-related papers by Haoran Du, Jiongzhe Su, and Keyang Zhang are accepted as oral presentations at the Design, Automation and Test in Europe Conference (DATE 2026). Their work presented spintronic flip-flops in RISC-V Platform, dual-port SOT-MRAM, and OTP BCAM for DDR4 STT-MRAM redundancy. 

[TCAS-I'2025]. 11/2025: The MRAM-MCU (DOI: 10.1109/TCSI.2025.3636931) and 500MHz SOT-MRAM (DOI: 10.1109/TCSI.2025.3631103) work led by Haoran Du and Zhenghan Fang are accepted by IEEE Trans. on Circuits and Systems I: Regular Papers. Their works present STT-MRAM achieving >10^9-cycle endurance across -40°C to 125°C has been developed for use in microcontroller units, and a dual-path SOT-MRAM achieving 500-MHz read and 100-MHz write. 

[TR'2025]. 11/2025: OTP-MRAM led by Jiongzhe Su is accepted by IEEE Trans. on Reliability. This work presents a versatile one-time-programmable STT-MRAM for security-aware scenario. 

[IEDM'2025]. 09/2025:  A collaborative work with HKUST, led by Yaoru Hou is accepted by IEDM. This work proposes a fully analog in-memory Ising machine based on VCMA-MTJ technology. By integrating deterministic and probabilistic computation in one device, the 28‑nm CMOS‑based chip achieves up to 73.7× higher spin density and only 28 μW/spin, cutting power by 2.46–147× compared to previous designs.

[TED'2025]. 06/2025: MRAM TCAM led by Hongjin Zhu is accpted by IEEE Trans. Electron Device. This work presents a 6T-4MTJ SOT-based memory cell. Achievements include an 8.5× increase in match-line voltage swing, a soft error rate below 0.1%, and an energy consumption of only 3 fJ per search at 0.8 V. Using a TLFA technique, the design maintains high search reliability at 0.6V VDD.

[EDL'2025]. 06/2025: OTP models led by Jiongzhe Su is accepted by IEEE Electron Device Letters. Twin models for MTJ reliability are proposed: one optimizes endurance versus write error rate, and another refines hard-breakdown probabilities. Based on experimental data, these models enable a demonstrated 4-Mb STT-MRAM subsystem.

[CICC'2025]. 04/2025: 40nm STT-MRAM for mass production, led by Yaoru Hou is accepted by CICC. This work presents a 4Mb high-reliability STT-MRAM achieving 18ns write-time and 94.9% wafer-level-die-yield across -55°C-to-125°C.

主持国家自然科学基金、国家重点研发计划课题、江苏省基础研究专项

https://scholar.google.com/citations?user=PUgTVY8AAAAJ&hl=zh-CN

IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), Associate Editor (编委)

IEEE Transactions on Very Large Scale Integration Systems (T-VLSI), Associate Editor (编委)

Journal of Semiconductors, Editor (编委)

2022-2026 ACM/IEEE Design Automation Conference (DAC) Technical Program Committee

IEEE CASS Nanoelectronics and Gigascale Systems (Nano-Giga) 分会技术委员

员工获奖：博士生获首届中国电子学会集成电路一等奖学金（2020），4人获IEEE国际会议最佳论文奖，1人获bevictor伟德官网至善优博奖励计划（2024），2人获江苏省优秀本科毕业设计（2021，2024）

课外研学：指导员工获互联网+全国银奖、全国老员工嵌入式芯片与系统设计竞赛全国一等奖

毕业生去向：高校教职、海外读博（HKUST，U-MACAO，U-OSAKA）、长鑫、长存、兆易、海光、华为海思，字节跳动，中国电科、英伟达、恩智浦