- 2016 - 2020：美国德克萨斯理工大学 （Texas Tech University），计算机科学（博士）

- 2014 - 2016：美国德克萨斯理工大学 （Texas Tech University），计算机科学（硕士）

• 2024.4 - 至今：  bevictor伟德官网，bevictor伟德官网，副教授

• 2024.1 - 2024.4：国家集成电路自动化设计技术创新中心，大模型项目组，项目主管

• 2023.6 - 2024.1：清华大学，深圳国际研究生院，项目研究员

• 2021.5 - 2023.5：清华大学，深圳国际研究生院，博士后研究员

• 2018.5 - 2018.8：美国西北太平洋国家实验室（Pacific Northwest National Laboratory），High-Performance Computing Department，博士实习（Ph.D. Intern）

• 2017.5 - 2017.8：美国阿贡国家实验室（Argonne National Laboratory），Mathematics and Computer Science Division ，科研助理（Research Aide）

• 2016.5 - 2016.8：美光科技（MicronTechnology, Inc.），Advanced Memory System Group，编译器工程师（Compiler Engineer）

研究专注于AI+IC以及AI+EDA方向，包括：数字芯片自动化设计验证大模型，智能EDA，处理器设计，计算机体系结构，大语言模型，编译器，二进制转译，高性能计算，并行计算，敏捷开发工具链等方向。

论文发表

• Jia Xiong, Runkai Li, Haowen Fang, Cheng Ni, Ziran Zhu, Nan Guan, Zhe Jiang and Xi Wang, ParetoPilot:Global Optimization Reasoning on HLS Design Space Exploration with LLMs, IEEE DAC 2026

• Lik Tung Fu, Jie Zhou, Shaokai Ren, Mengli Zhang, Nan Guan, Zhe Jiang and Xi Wang, ChatSVA: Bridging SVA Generations for Hardware Verification via Task-specific LLMs, IEEE DAC 2026

• Jieran Cui, Zhengkai Wen, Haowen Fang, Yinan Zhu, Jia Xiong, Cheng Ni, Mingchi Zhang, Nan Guan and Xi Wang, ZK-Tracer: A High-Performance Heterogeneous Accelerator for Zero-Knowledge VM Trace Generation, IEEE DAC 2026

• Qiyuan Chen, Fuxing Huang, Lixin Chen, Hao Wu, Hao Gu, Xiqiong Bai, Xi Wang and Ziran Zhu, Toward True-3D Timing-Driven Analytical Global Placement for Mixed-Size Face-to-Face 3D ICs, IEEE DAC 2026

• Jianmin Ye, Yifan Zhang, Tianyang Liu, Qi Tian, Shengchu Su, Lik Tung Fu, Nan Guan, Zhe Jiang and Xi Wang, LLM-Aided Reference Model Design for Agile Hardware Verification, IEEE DAC 2026

• Yuchen Hu, Jialin Sun, Yushu Du, Renshuang Jiang, Ning Wang, Weiwei Shan, Xinwei Fang, Xi Wang, Nan Guan and Zhe Jiang, Beyond Fuzzer Islands: CPU Fuzzing via Smart Coordination, IEEE DAC 2026

• Ning Wang, Zichong Deng, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Zhe Jiang and Nan Guan, CircuitDiff: Bridging Netlist Knowledge with RTL based on Graph Denoising Diffusion, IEEE DAC 2026

• Junhao Ye, Dingrong Pan, Hanyuan Liu, Yuchen Hu, Jie Zhou, Ke Xu, Xinwei Fang, Xi Wang, Nan Guan and Zhe Jiang, UVMarvel: an Automated LLM-aided UVM Machine for Subsytem-level RTL Verification, IEEE DAC 2026

• Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Zhe Jiang and Nan Guan, Insights from Verification: Training a Verilog Generation LLM using Reinforcement Learning with Testbench Feedback, IEEE DAC 2026

• Wan, Gwok-Waa and Su, Shengchu and Zhang, Jingyi and Wong, Sam Zaak and Xing, Mengnv and Ji, Lei and Jiang, Zhe and Wang, Xi and Yang, Jun, ChatTest: Coverage-Enhanced Testbench Generation for Agile Hardware Verification with LLMs, IEEE DATE 2026.

• Changwen Xing, SamZaak Wong, Xinlai Wan, Yanfeng Lu, Mengli Zhang, Zebin Ma, Lei Qi, Zhengxiong Li, Nan Guan, Zhe Jiang, Xi Wang, Jun Yang, ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications, AAAI 2026

• Chenxu Niu, Wei Zhang, Jie Li, Yongjian Zhao, Tongyang Wang, Xi Wang, Yong Chen, TokenPowerBench: Benchmarking the Power Consumption of LLM Inference, AAAI 2026

• Gwok-Waa Wan, Shengchu Su, Ruihu Wang, Qixiang Chen, Sam-Zaak Wong, Mengnv Xing, Hefei Feng, Yubo Wang, Yinan Zhu, Jingyi Zhang, Jianmin Ye, Xinlai Wan, Tao Ni, Qiang Xu, Nan Guan, Zhe Jiang, Xi Wang, Yang Jun, FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification, AAAI 2026

• Qiang Xu, Leon Stok, Rolf Drechsler, Xi Wang, Grace Li Zhang, Igor L Markov, Revolution or Hype? Seeking the Limits of Large Models in Hardware Design, IEEE ICCAD 2025.

• Chenchen Zhao, Zhengyuan Shi, Xiangyu Wen, Chengjie Liu, Yi Liu, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqi Fu, Chujie Chen, Chenhao Xue, Ying Wang, Yibo Lin, Jun Yang, Ning Xu, Xi Wang, Qiang Xu, MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs, IEEE ICCAD 2025.

• Junhao Ye, Yuchen Hu, Ke Xu, Dingrong Pan, Qichun Chen, Jie Zhou, Shuai Zhao, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang, From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification, IEEE ICCAD 2025.

• Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan, Xi Wang, Nan Guan, Zhe Jiang, Location is Key: Leveraging LLM for Functional Bug Localization in Verilog Design, IEEE DAC 2025

• Yuchen Hu, Junhao Ye, Ke Xu, Jialin Sun, Shiyue Zhang, Xinyao Jiao, Dingrong Pan, Jie Zhou, Ning Wang, Weiwei Shan, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang, Xi Wang, Nan Guan, Zhe Jiang, UVLLM: An Automated Universal RTL Verification Framework Using LLMs, IEEE DAC 2025.

• Juxin Niu, Xiangfeng Liu, Dan Niu, Xi Wang, Zhe Jiang, Nan Guan, ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection, IEEE DAC 2025.

• Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Zhe Jiang, Nan Guan, Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning, IEEE ICLAD 2025.

• Ning Wang, Bingkun Yao, Jie Zhou, Yuchen Hu, Xi Wang, Zhe Jiang, Nan Guan, VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction, IEEE ICLAD 2025.

• Zeju Li, Changran Xu, Zhengyuan Shi, Zedong Peng, Yi Liu, Yunhao Zhou, Lingfeng Zhou, Chengyu Ma, Jianyuan Zhong, Xi Wang, Jieru Zhao, Zhufei Chu, Xiaoyan Yang, Qiang Xu, DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis, IEEE ICLAD 2025.

• Yibo Rui, Yuanhang Li, Rui Wang, Ruiqi Chen, Yanxiang Zhu, Zhixiong Di, Xi Wang, Ming Ling, ChaTCL: LLM-Based Multi-Agent RAG Framework for TCL Script Generation, IEEE ISEDA 2025.

• J Li, SZ Wong, GW Wan, X Wang, J Yang, EDA-Debugger: An LLM-based Framework for Automated EDA Runtime Issue Resolution,IEEE ISQED 2025.

• Ke Xu, Jialin Sun, Yuchen Hu, Xinwei Fang, Weiwei Shan, Xi Wang and Zhe Jiang, MEIC: Re-thinking RTL Debug Automation using LLMs, IEEE ICCAD 2024.

• Xi Wang, Gwok-Waa Wan, Sam-Zaak Wong, Layton Zhang, Tianyang Liu, Qi Tian and Jianmin Ye, ChatCPU: An Agile CPU Design & Verification Platform with LLM, IEEE DAC, Best Paper Award Nominee (5/1456),  2024

• Gwok-Waa Wan, Sam-Zaak Wong, Xi Wang, Jailbreaking Pre-trained Large Language Models Towards Hardware Vulnerability Insertion Ability, ACM/IEEE GLVLSI 2024.

• Tianyang Liu, Qi Tian, Jianmin Ye, LikTung Fu, Shengchu Su, Junyan Li, Gwok-Waa Wan, Layton Zhang, Sam-Zaak Wong, Xi Wang, and Jun Yang，ChatChisel: Enabling Agile Hardware Design with Large Language Models，ISEDA 2024.

• Yuxuan Du, Zhengguo Shen, Junyi Qian, Chengjun Wu, Weiwei Shan, and Xi Wang, DSC-TRCP: Dynamically Self-calibrating Tunable Replica Critical Paths Based Timing Monitoring for Variation Resilient Circuits, IEEE JSSC, 2024. 

• Cai Li, Haochang Zhi, Kaiyue Yang, Junyi Qian, Zhihao Yan, Lixuan Zhu, Chao Chen, Weiwei Shan, and Xi Wang, A 0.61μW Fully-Integrated Keyword-Spotting ASIC with Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN, IEEE JSSC, 2023.

• Xi Wang, John D. Leidel, Brody Williams, Alan Ehret, Miguel Mark, Michel Kinsy, and Yong Chen, xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing, IEEE Conference on International Parallel & Distributed Processing Symposium (IPDPS), Best Paper Award (1/462), 2021. 

• Xi Wang, Antonino Tumeo, John D. Leidel, Jie Li and Yong Chen, HAM: Hotspot-Aware Manager for Improving Communications with 3D-Stacked Memory, IEEE Transactions on Computers (TC). 

• Zach Hansen, Brody Williams, John D. Leidel, Xi Wang, Yong Chen, DMM-GAPBS: Adapting the GAP Benchmark Suite to a Distributed Memory Model, IEEE High Performance Extreme Computing Conference (HPEC), 2021.

• Brody Williams, John D. Leidel, Xi Wang, and Yong Chen, CircusTent: A Benchmark Suite for Atomic Memory Operations, ACM International Symposium on Memory Systems (MEMSYS), 2020.

• John D. Leidel, Xi Wang, Brody Williams, and Yong Chen, Toward a Microarchitecture for Efficient Execution of Irregular Applications, ACM Transactions on Parallel Computing (TOPC), 2020. 

• Xi Wang, John D. Leidel, Brody Williams, and Yong Chen, PAC: Paged Adaptive Coalescer for 3D-stacked memory, ACM High-Performance Parallel and Distributed Computing (HPDC), 2020. 

• Xi Wang, Brody Williams, John Leidel, et al., Remote Atomic Extension (RAE) for Scalable High Performance Computing. IEEE Design Automation Conference (DAC), 2020. 

• Xi Wang, Antonino Tumeo, John D. Leidel, Jie Li, and Yong Chen, MAC: Memory Access Coalescer for 3D-Stacked Memory, ACM International Conference on Parallel Processing (ICPP), 2019.

• Jie Li, Xi Wang, Antonino Tumeo, Brody Williams, John D. Leidel, and Yong Chen, PIMS: A Lightweight Processing-in-Memory Accelerator for Stencil Computations, ACM International Symposium on Memory Systems (MEMSYS), 2019

• Xi Wang, John D. Leidel, Yong Chen, Memory Coalescing for Hybrid Memory Cube, ACM International Conference on Parallel Processing (ICPP), 2018.

• IEEE DAC 2024 Best Paper Award Nominee (5/1456)

• IEEE VLSI 2024 “Code-a-Chip” Award, First Prize

• CSAW 2023 International AI Hardware Attack Challenge, First Prize

• IEEE ISSCC 2023 “Code-a-Chip” Award, First Prize

• IEEE Conference on IPDPS 2021 Best Paper Award (1/462)

• Best Research Poster Award of NSF CAC (Cloud and Autonomic Computing) in 2020

• Helen DeVitt Jones Excellence in Graduate Teaching Award of Texas Tech University in 2018

• Travel Grant for attending ACM/IEEE SC17 (Super Computing 2017) in Denver 2017

• Travel Grant for attending ACM/IEEE SC16 (Super Computing 2016) in Salt Lake City 2016

🌊 团队愿景：数字芯片的“一键生成”！

GEAR（ Group of Emerging Architecture Research）自2023年起深耕基于AI大模型的芯片自动生成，专注于前沿芯片架构和芯片设计验证自动化（LLM + IC/EDA）的深度融合，实现AI设计芯片，芯片加速AI的”智芯“互联。

在通用人工智能（AGI）席卷全球的今天，传统的芯片设计模式正面临自硬件描述语言诞生以来最剧烈的震荡。过去四十年，芯片设计本质上是设计和验证的“人力的堆砌”。而今天，当大模型开始自主生成高质量代码、自动修复验证漏洞、甚至介入架构的决策时，芯片行业的结构性颠覆已经拉开序幕。

趋势需要被验证，方向需要被落地。我们的路径，是持续演进的系统工程实践：

2023.04 — 实现了全球首个利用 LLM 生成的 RISC-V CPU（4万门规模）

2024.06 — 发布 ChatCPU智能体平台，并生成了8万门规模的RISC-V CPU芯片，荣获EDA顶会IEEE DAC 2024 年度最佳论文提名

2025.01 — 发布 ChatDV，全球首个端到端芯片验证大模型智能体，芯片开发效率提升10倍

2025.08 — 基于AI智能体演进，成功生成超 400万门规模、11级流水线、乱序多发射的高性能 RISC-V 处理器芯片

⚙️ 团队哲学：每一颗齿轮都在驱动未来 -- Every Cog in the GEAR Counts!

There is no loser in a winning team，我们相信团队的胜利是个人成长的最强杠杆，因此我们关注每一位团队成员的未来发展。我们以Top-Down的教育方式辅助全栈式的芯片设计流程学习，鼓励系统思维与跨领域交叉探索，平衡 Research 与 Engineering，支持成员在前沿学术平台与真实产业系统中协同成长。在这里，每一颗齿轮都拥有独立的动力源，我们致力于培养在 AI 时代具备系统认知、工程能力与战略判断力的 IC 六边形人才。

🎯 我们在寻找改变时代的合伙人！长期招收博士、硕士研究生及本科科研训练员工，我们围绕 LLM + IC 的深度融合展开研究，重点方向包括：

1）芯片设计与验证大模型

2）芯片设计左移与PPA预测

3）芯片后端物理设计优化及EDA智能体设计

4）GPU/NPU算子生成、编译优化与二进制转译

5）大模型、强化学习以及Agentic协作系统

如果你认同 LLM 正在重塑芯片设计的未来 --- 

与其预见未来，不如亲手构建未来。

欢迎加入 GEAR，详情请通过邮件沟通咨询（ 📧 xi.wang@seu.edu.cn）。